During the process of developing a circuit design, the behavior of the design is simulated based on a specification of the circuit design. Simulating the design helps to verify correct behavior prior to physical implementation of the circuit. Wasted manufacturing costs due to faulty design may thereby be avoided.
Numerous tools are available for simulating circuit designs including, for example, high-level modeling systems (HLMSs). Co-simulation may also be used when the design may be more efficiently simulated by simulating different parts of the design on different simulation platforms (“co-simulation platforms”).
Example co-simulation platforms include both software-based and hardware-based systems. In a software-based system, a portion of the design is emulated with software running on a workstation, for example. In a hardware-based system, a portion of the design is emulated on a hardware platform that includes a programmable logic device (PLD), such as a field programmable gate array (FPGA). Co-simulation using a hardware platform may reduce the time required for a simulation run. The Modelsim simulator and the NC-SIM simulator from Cadence are example software-based systems, and the Wildcard development platform from Annapolis Microsystems and the Benone development platform from Nallatech are example hardware-based systems. The WildCard and Benone platforms are often used for algorithm exploration and design prototyping.
Most design tools recognize and support a hierarchical specification of the design, which allows the design to be specified and viewed at different levels of abstraction. The term “block” is sometimes used to refer to a collection of parts of a design that perform a function. Blocks consume inputs and produce outputs as a function of internal state, blocks are connected by arcs, and arcs conduct data between blocks. At some level in this hierarchical framework, simulating the design involves moving data from one block of the design to another block of the design.
An HLMS, such as System Generator for DSP (Sysgen) HLMS, may permit a block of a circuit design to be translated into PLD configuration data that may be used to configure a hardware-based co-simulation platform. The HLMS may include a “hardware co-simulation block” as a proxy for the hardware-based co-simulation platform. Like other blocks of the circuit design, the hardware co-simulation block consumes inputs and produces outputs. The hardware co-simulation block transfers the inputs for the block from the HLMS to the hardware-based co-simulation platform and transfers the outputs of the block from the hardware-based co-simulation platform to the HLMS.
The transfer of data, such as input values and output values for a block, between the HLMS and the hardware-based co-simulation platform may have substantial overhead, such as software overhead to setup the data transfer and hardware overhead to perform the data transfer. Multiple transactions may be required to transfer data for each HLMS simulation cycle, and each transaction typically may transfer a small amount of data, such as 32 bits.
The overhead associated with the data transfer between the HLMS and the hardware-based co-simulation platform often limits the performance for the simulation. For example, performance may be severely impacted in simulating a system requiring large amounts of data transfer, such as real-time signal processing applications including video and image processing.
The present invention may address one or more of the above issues.